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Digital SoC Design

Empyrean provides SOC designers with solution to clock tree simplification and optimization, timing signoff automation and lib files analysis. Challenges in clock tree optimization and timing signoff come along with multi-scenario design methodology in progressive process, increasing difficulty of clock implementation and uncertainty to turn-around-time .

With powerful built-in engine, Empyrean could help engineers in clock tree optimization analyze clock structure, find potential problems, improve clock tree quality, and then enhance frequency, reduce power cost in clock network. To meet tight TAT in timing signoff stage, Empyrean supplies an integrated solution to hold/setup/trans fix with golden timing accuracy and smart automatic placement, which efficiently speed up timing signoff process and help designers deliver products on schedule.