ClockExplorer analyzes clock structures and optimizes clock constraints to reduce insertion delay. The generated constraints are CTS-aware, enabling better clock tree generation. ClockExplorer also provides a comprehensive set of checking capabilities which are used by both the front-end and back-end design teams as a tool for sign-off/sign-in of clock constraints.   

Key Benefits: 

  • Providing front-end sign-off checks prior to netlist delivery
  • Automatically identifying potentially hazardous clock structures
  • Verifying manually-written CTS constraints
  • Generating optimized CTS constraints
  • Automatic clock schematic generation
  • Seperating timing-independent skew groups
  • Removing invalid clock paths


  • Reduces clock insertion delay by up to 50%
  • Lowers clock power
  • Reduces CTS design cycle
  • Speeds up timing closure

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