RCExplorer is an on-chip interconnect parasitic extraction and analysis tool for Analog, AMS and Digitial designs. RCExplorer generates distributed 3D capacitance and resistance including advanced manufacturing effects associated with 45nm processes and below. RCExplorer also provides easy-of-use functionalities for interconnect analysis after extraction. RCExplorer is intergrated with leading layout tools for both batch-mode and interactive usage.

 

Key Benefit

  • Enable parasitic extraction and analysis through all design stages

  • Reduce design iteration time by enabling ealry layout simulation through early stage parasitic extraction

  • Quickly analyze interconnect effect by probing interconnect in existing layout environment

 

Key Features

  • Employ state-of-art 3D field solver to achieve highest accuracy interconnect resistance and capacitance modelling on complex geometries

  • Support un-routed and partial-route net extraction with built-in routing engine

  • Advanced interconnect analysis capabilities such as pin-to-pin resistance analysis, point-to-point-to resistance analysis, net parasitic bottleneck analysis and pin-to-pin delay analysis etc

  • Integrated into leading layout tools for both interactive and batch-mode usage

  • Support both P-Cell and PyCell

  • Support both flatten and hierarchical designs


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