2018-06-24 / DAC 2018 / San Francisco, CA, US
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Dear friends and partners,

Design Automation Conference (DAC), the premier conference for design and automation, will take place on June 24-28 in San Francisco, USA.

As an emerging vendor of electronic design automation solution, Empyrean will highlight the strength in True-Spice circuit simulation, yield enhancement, PPA optimization, SerDes IP and new display panel design solution at this muscle-flexing event.

Welcome to the grand conference and visit our booth and meet us there!


Booth:1449 
Date: June 24-28,2018
Venue:MOSCONE CENTER - WEST HALL - SAN FRANCISCO, CALIFORNIA
 


Our Oral Presentation on  Designer Track :

'Fast Timing Data Analysis for better Performance, Power and Area on High Performance Computing Design’

DAC’S COMMENTS:
  • "This presentation describes a flow for library analysis and cell selection for use in a high-performance CPU design. Results demonstrate the effectiveness of the selection strategy."
  • "This is very useful feature. We spent lots of time to come to analyze the cells that to be used in synthesis/placement/cts/timing-eco and don't use cells. It takes lots of effort to gather that information before the flow is setup. Good tool to take a look when setting up the flow for new technology node."
  • "This topic is something we've considered in the past, but haven't done any scientific study/experiments to figure out exactly what we should use...mostly just anecdotally tried things and used a combination that worked."
  • "Excellent Methodology to analyze library cells across drive/Vt for PPA. Automation and reporting is great efficiency improvement."
Our Poster Presentation on  Designer Track:
  1. Fast Library Evaluation Method based on Static Liberty Comparison
  2. A Smart Layout Merging and Review Flow for Multi_core Server CPU Design
  3. A High Efficiency SPICE Accuracy Timing Closure Flow
  4. Efficient MCMM Timing ECO on Hierarchical SoC Design with Multiple Variable Voltage Domain
  5. Spice based Big Data Analysis for Optimal Timing Signoff on IoT Design.
  6. A New IP Layout Review and Evaluation Flow
  7. Performance Prediction with Varied Voltage for High Performance Computing Design

Looking forward to seeing you at DAC 2018 in San Francisco!