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A New Generation of Simulator ALPS Released on Empyrean Technical Seminar(SZ)
2015-11-20 16:17:00   来源:   报名:0 点击:

(Shenzhen, November 20, 2015) 2015 Empyrean Technical Seminar was held at Ruanjian Building, Shenzhen. The Seminar, organized by Shenzhen Semiconductor Industry Association and carefully guided by National IC Design Shenzhen Industrial Center (Shenzhen ICC), has invited many technical experts from Shenzhen HiSilicon, ZTE Vimicro, Solomon Systech and other corporations to participate in the research and discussion.
ZHOU Shengming, director of National IC Design Shenzhen Industrial Center, comprehensively and thoroughly introduced localization services of ICC combining with Empyrean domestic EDA tools and IP, and shared the analysis about status and trends of the IC design field in south China.
In this seminar, DONG Senhua, general manager of the Physical Design Department of Empyrean, officially released a new generation of 10nm high-speed parallel stimulator---ALPS, which has been successfully testified in Solomon Systech, greatly improving the simulation efficiency; a comprehensive discussion was made about the solution of digital SoC design optimization.
A New Generation of High-Speed Full-chip Stimulator---ALPS
With the development of advanced process nodes, IC design has become more and more complicated and especially the scale of parasitic devices of post-layout simulation circuits has become larger and larger. Using the new exclusive generation of the smart matrix solver, Empyrean provides the high-accuracy, high-performance and high-capacity parallel spice stimulator---ALPS. In terms of the large-scale post-layout simulation design, compared with current leading commercial simulators in the market, ALPS can provide several to tens of times of speedup so as to significantly shorten the cycle of IC product development.
High Accuracy
Without using the traditional fast-spice technique or any model simplification technology, ALPS can guarantee the True-SPICE-Level accuracy by solving the whole-circuit equation and strictly observing the convergence criterion and step-control means of Spice.
High Performance
Traditional simulators add the parallel technique to the original frame; however, ALPS is based on parallel frame development so as to assign parallel tasks better, which is good for large-scale parallel calculation. Meanwhile, ALPS adopts the exclusive smart matrix solver technique, automatically selecting the most suitable matrix solver based on characteristics of the matrix, which greatly reduces time of the matrix solution with performance far beyond the leading commercial simulators. It is especially suitable for large-scale analog circuit post-layout simulation application.
High Capacity
With the advanced and efficient memory management means, ALPS can be applied to the top-level True-SPICE simulation of 10 millions of transistors.
In addition, the senior engineer YANG Yuhui from HiSilicon, the famous back-end expert LI Jian from ZTE Vimicro, the senior engineer CHEN Zhirong, Design Manager LV Xiaokang from Solomon Systech and other technical experts shared cases about the extremely fast chip-finishing layout platform Skipper; library/IP QA & debugging platform Qualib; clock, timing and power optimization resolution ICExplorer (including ClockExplorer\TimingExplorer\PowerExplorer).
This year, the high-speed interface and ultra-low power consumption IP of Empyrean has been launched on the IP platform provided by Shenzhen ICC, which offers more convenient localization services to Shenzhen chip design corporations.
For more EDA solutions and IP information, please visit http://www.empyrean.com.cn
[Upcoming Event] In the upcoming 2015 ICCAD on December 10, Empyrean is to display above mentioned EDA and IP solutions. IC design engineers can keep close attention and welcome to the conference!

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