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Next Generation Timing Closure and Silicon-aware Timing Sign-off
2017-05-22 16:26:20   来源:   报名:0 点击:


Right before the opening of  54th DAC, China based EDA vendor Empyrean  launched the next generation timing closure solution ICExplorer-XTop and SPICE level accurate Silicon-aware timing sign-off solution ICExplorer-XTime. Those two solutions can effectively improve the efficiency of advanced SoC designs, achieve the best chip performance, power and area (PPA), and significantly improve the yield.

The optimization and improvement of existing ICExplorer architecture and algorithms have significantly boosted ICExplorer performance and improved QoR results. However, it is the capability of  “Silicon Sign-off” solution makes ICExplorer revolutionary.

ICExplorer-XTop is a new generation of timing optimization solution. With the solid foundation of physical aware technology, it boosts its performance through parallelization that multi-objective timing optimization can be achieved in much shorter time for adanced 16nm/14nm/10nm FinFET process. It reduces the turnaround time of each design iteration.

The Key technologies including:

    Advanced Massively Parallel Architecture
       To handle huge scale hierarchical designs with +100M instances and +100 scenarios.
       Support save/restore sessions and incremental design setup

     New timing analysis engine, based on large data mining and AI algorithm (AOCV/POCV/SBOCV supported, provide more accurate timing propagation)
       New physical analysis engine, support the physical constraints of advanced technology and better handle the congestion problems

     Powerful timing inspection and interactive ECO
        Help designers quickly fix the last phase of hot-paths.
        Excellent GUIs for layout browsing, timing path inspection, interactive ECO and reports lead to the extreme user experience.

SPICE level accurate Silicon-aware timing sign-off solution ICExplorer-XTime, effectively solves the timing convergence problem in the process of advanced technology or low voltage design, which is caused by inaccurate timing calculation of STA tools. The built-in super-fast SPICE simulation engine (ALPS™) with advanced Smart Matrix Solver technology can provide 5-10X acceleration compared to the traditional simulator.

The super parallel architecture (distribution + threads) can make full use of the hardware resources of the processor, and quickly complete the simulation and big data analysis of the results. There are abundant Silicon-aware sign-off features, such as timing calibration to identify true critical paths, V/T sweep to analyze low V/T limitation and design sensitivity, fast Monte-Carlo analysis for high yield analysis.

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