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华为海思

华为海思应用九天SOC设计解决方案加速设计收敛

"Practically speaking, every SOC design closure takes not only a significant amount of time and effort, but multiple iterations as well. Using Empyrean’s physically-aware timing tool TimingExplorer, and Skipper their chip finishing capability, we reduced the number of iterations by at least 50% on each SOC design. And we have reduced clock tree power by almost 40% in one of multimedia chip using optimized clock constraints generated from TimingExplorer. "
 
— Yu Xia, Senior Physical Design Manager,Hisilicon

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