2016-06-06 / DAC 2016 / Austin,Texas,US
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Dear Friend,
 
Visit our booth 738  to see how our EDA solutions validate and improve your design quality, boost your design simulation, and accelerate your design closure.  Also, see how our silicon proven IP solutions could be customized for your special tape out needs.

EDA Highlights
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- ClockExplorer
   
Rule based  SOC Clock Sign-off and Sign-In Enable Better Clock Quality
- TimingExplorer
    16nm and below Tape-out Proven Timing Closure 
- Skipper
    Fast One-Stop Layout Review, Analysis and IP Protection Platform
- Qualib
    A Comprehensive IP/STD QA Platform for Better Quality and Higher Productivity
- ALPS
    Parallel True SPICE to Super Charge Post-Layout Simulation

Silicon Proven IP For High Speed Interface
SATA  PCIE   USB  DDR   HDMI / MHL
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