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2015Q3 Product Release Training

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对象 : Global Agents

时间 : 2015-09-11 09:00:00

时长 : 2h

主讲人(组织者):Michael Liu(刘晓明)


概述:Learn about the new features and enhancements in ALPS, ClockExplorer, Skipper and Qualib that meet the challenge of high-speed and low-power design and optimization
详细介绍:

 
Welcome to attend the training conference.Please click the Blue button\ to register.
The host will send  the Webinar link to your mail address later.
 


 

ALPS
随着先进工艺结点的发展,IC设计变得越来越复杂,尤其是后防电路的寄生器件规模越来越大。华大九天利用独有的新一代smart matrix solver,提供了一个高精度、高性能、高容量的并行spice仿真工具ALPS。 对于大规模的post-layout设计,与目前市场的主流商用仿真工具相比,ALPS具有数倍到十数倍的加速效果,可大幅缩短IC产品开发周期。
 

  • Accuracy-- True-SPICE engine ( no cheating with fast-spice technology)
  • Capacity-- Able to handle post-layout flatten circuit with +10M elements 
  • Performance-- ~5X-10X speed up for post-layout simulation
  • Scalability-- 5X comparing to 2-3X ( competing tools) with 8 threads  

Skipper
Skipper是针对Tape-out阶段版图处理的一套工具组合。不同于传统工具,针对所要处理的大规模数据,除高速读入数据、快速查看外,对版图处理中常用的版图比较、连接关系提取、图形Boolean操作、IP merge等功能在处理方式上做了特殊的优化,可以给用户带来高效、全新的使用体验。

Highlights

•One of the fastest tools for importing and viewing layout data
•Large data handling capacity—over 100GB GDS
•Integrated chip-finishing platform
•Layout editing, net tracing, and Boolean operations
•Comprehensive search mechanisms
•Fastest layout comparison—design and mask data
•DRC/LVS debugging
•Cell swapping and IP merging
•Focused ion beam (FIB) data processing
•3D viewing for layout inspection

ClockExploer
承担起前段设计与后端设计的桥梁,清晰展示复杂时钟系统结构,自动分析不优化的时钟结构和约束,缩短设计周期,提高设计质量。

 
Benefits
¤Better design methodology for clock quality checking
¤Better clock design understanding and communication for frontend and backend teams
¤Fewer clock design and CTS iterations and better CTS quality
¤Optimize clock latency and power
 

Qualib
Qualib是一个检查库单元及IP模块质量的平台产品。随着工艺节点进入28nm/20nm,无论是单元或者IP库的设计者,还是库的使用者,都需管理复杂而又众多的单元或者IP库。如何保证单元或者IP库的正确性,不同view(例如网表,LEF,GDS等)之间的一致性和各版本之间的性能稳定性,愈发困难,已成为业界关注的焦点。

Key Features

•Integrity checking
–Layout (GDS)
–Physical Model (LEF)
–Timing Model (Liberty)
–Netlist (Verilog)
•Consistency checking
–LEF vs. GDS
–LEF vs. Liberty
–LEF vs. Verilog
–Liberty vs. Verilog
•Version comparing
–Timing
–Power
–Area
•Fast run time
•Easy debugging

 

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